d-Matrix is a US startup that designs AI inference accelerators. Its Corsair inference accelerator entered volume production on June 9, 2026 (Source: theinformation.com).
On July 7, 2026, d-Matrix and Nvidia disclosed a partnership combining their respective hardware in a new system to power AI models. The Information characterized the arrangement as the latest example of Nvidia's strategy of partnering with, rather than fighting, its growing list of AI server-chip competitors — a pattern that includes vendor-financing and backstop arrangements with cloud providers deploying non-Nvidia silicon (Source: theinformation.com).
Products
Corsair, presented at Hot Chips 2025, is an in-memory-computing inference accelerator built on SRAM. In d-Matrix's own account, a pair of Corsair cards reaches roughly 300 TB/s of memory bandwidth at about 1 ns latency but holds only about 4 GB, which the company says suits SRAM designs to small models such as the draft model in speculative decoding rather than to holding frontier-model weights. The company has also shown a networking product, the JetStream 400G Ethernet card, for data-center-scale inference (Source: servethehome.com).
Raptor, presented at Hot Chips 2026 in August 2026, is d-Matrix's next design. It stacks a TSMC N4 logic die directly on a 3D DRAM die using 36 µm face-to-face bonding, an approach the company presents as an alternative to high-bandwidth memory (HBM). d-Matrix argues that HBM4 packages such as Nvidia's Vera Rubin and AMD's Instinct MI455 face a practical bandwidth ceiling of around 20 TB/s set by package edge space and power, and that vertical 3D I/O costs about 0.3 to 0.4 pJ per bit, roughly a tenth of HBM. The company's stated figures for Raptor are 32 GB per card; about 32.6 GB/s of bandwidth per square millimetre against roughly 1.5 GB/s for HBM4 and Nvidia's Rubin R200; 2.96 mW per GB/s against 40 mW; a 72-card scale-up able to host a frontier model such as Kimi K3 at a 1-million-token context in one rack, with 4-bit weights and an 8-bit KV cache; and roughly 1,000 tokens per second per user serving a 3-trillion-parameter-class model at 1-million-token context. ServeTheHome, which covered the presentation live, reported the figures as the company's claims and noted that d-Matrix said little about the design's drawbacks and had not shown it running (Source: servethehome.com).
Market position
d-Matrix operates in the same custom-inference-silicon segment as Groq, Cerebras, and the hyperscaler ASIC programs co-designed by Broadcom, a segment whose growth bears on inference economics and on competition questions about concentration in the compute stack.
Relationships
- related: Nvidia & TSMC — AI Compute Infrastructure — July 2026 hardware partnership
- related: Groq, Cerebras Systems, Broadcom — inference-silicon segment peers
- related: Inference Economics and Token Pricing — inference accelerators shape serving costs
- related: Kimi K3 — the frontier model d-Matrix used to size a single Raptor rack