Ascend is Huawei Technologies' line of AI accelerators, designed by its HiSilicon arm and fabricated primarily by SMIC. Built to supply Chinese AI compute after US export controls restricted Nvidia sales into China, the program spans the Ascend 910B and 910C chips, the 950 series, and the CloudMatrix rack-scale systems. Its design integrates HiSilicon chip design, SMIC fabrication, CXMT/Swaysure memory, and proprietary CloudMatrix networking, and its production scale is constrained by high-bandwidth memory (HBM) supply rather than logic dies.
| Field | Value |
|---|---|
| Type | AI accelerator program inside Huawei Technologies |
| Country | China (Shenzhen) |
| Design arm | HiSilicon |
| Fabrication partner | SMIC (enhanced 7nm-class, DUV multi-patterning); historical TSMC die bank |
| Key products | Ascend 910B, 910C, 950PR (Q1 2026), 950DT (Q4 2026); CloudMatrix 384 rack-scale system |
| Position | Dominant domestic AI accelerator supplier inside China post-export-controls |
Snapshot
Production ramp
| Year | Total Ascend | Of which 910C |
|---|---|---|
| 2024 | ~507k | (mostly 910B) |
| 2025 | ~805k | ~653k |
| 2026 (target) | ~1.6M dies | ~600k 910C |
(Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md.)
Investment commitments
| Date | Commitment | Detail | Source |
|---|---|---|---|
| 2026-04-24 | Up to $11.7B over five years on autonomous-driving compute | Includes $2.64B for autonomous-driving R&D in 2026 alone | (Source: scmp.com) |
Product roadmap
| Chip | Date | Process | Per-Die Perf | Memory | Notes |
|---|---|---|---|---|---|
| Ascend 910B | Shipping | SMIC 7nm / TSMC legacy | ~½ H100 BF16 | HBM2e | Volume workhorse through 2024 |
| Ascend 910C | Shipping (2025) | SMIC 7nm + TSMC die bank | ~⅓ Nvidia B200 BF16 | HBM3 (CXMT + smuggled Samsung) | 2026 target: 600k units |
| Ascend 950PR | Q1 2026 | SMIC 7nm | H100-class | HiBL 1.0 custom (128 GB, 1.6 TB/s) | Monolithic die; prefill / recommendation |
| Ascend 950DT | Q4 2026 | SMIC 7nm | ~Hopper/Blackwell-class | HiZQ 2.0 custom HBM (144 GB, 4 TB/s) | Training / decoding; 2 TB/s interconnect |
| Ascend 960 | 2027 | SMIC advanced | 2x 950DT | HBM-class | Chiplet; 30 EFLOPS FP8 / 60 EFLOPS FP4 supernode |
| Ascend 970 | 2028 | — | Rubin-class aspiration | — | Target 4 ZettaFLOPS FP4 supernode |
The 950 series supports the FP32, HF32, FP16, BF16, FP8, MXFP8, HiF8, MXFP4, and HiF4 data formats. It also adds SIMT support to improve CUDA compatibility, addressing an adoption barrier against CUDA/PyTorch codebases. Some earlier reporting used the names "910PR / 910DT"; the official Huawei Connect 2025 nomenclature, from the Xu Zhijun keynote, is 950PR / 950DT.
Tau Scaling Law and LogicFolding
At a Shanghai semiconductor symposium on May 25, 2026, Huawei described a chip-design principle it calls the "Tau Scaling Law," arguing that the industry can no longer rely on shrinking transistors (the Moore-Dennard scaling tradition) and should instead optimize for shorter interconnects and lower in-chip data-movement latency. Huawei paired the principle with a specific architecture it calls "LogicFolding." The company said 381 chips had already been mass-produced on Tau Scaling principles at the time of the announcement, that Kirin smartphone chips launching later in 2026 would be the first to use LogicFolding as the architectural primitive, and that Ascend AI chips would adopt LogicFolding by 2030. Huawei set a target of transistor density equivalent to 1.4-nm processes by 2031 without access to the leading-edge EUV lithography that US export controls deny SMIC. SMIC shares rose 7.6% on the announcement. (Source: reuters.com; bloomberg.com)
The roadmap describes a path that does not require EUV access, and the latency-optimization framing aligns with the inference-cost compression argument that Dario Amodei of Anthropic has emphasized as a scaling frontier (see AI cybersecurity). The symposium came alongside the government-to-government AI dialogue Xi Jinping and Donald Trump agreed to launch during Trump's May 2026 China visit. In the same week at Taipei, Nvidia CEO Jensen Huang said Nvidia has "largely conceded" China's AI-chip market to Huawei. (Source: reuters.com; bloomberg.com)
Fabrication and supply chain
TSMC die bank
Before the October 2020 entity-list tightening, Huawei/HiSilicon stockpiled more than 2.9 million advanced Ascend dies fabricated at TSMC. SemiAnalysis classifies this stockpile as an export-control violation, and it funded 2024 and most of 2025 production. TechInsights teardowns confirm that deployed 910C units still contain TSMC CPU dies dated 2020. (Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md.) Gregory Allen's CSIS report confirms via US government sources that TSMC manufactured 2 million-plus Ascend 910B logic dies for Huawei through shell companies, which Allen describes as a "strategically significant stockpile" and a direct export-control violation; SemiAnalysis's 2.9 million figure is consistent with, and higher than, Allen's more conservative government-sourced number. Allen assesses that the stockpile materially extended Huawei's runway through 2024–2025 (Gregory Allen's CSIS report).
SMIC collaboration
SMIC fabricates Ascend logic on an enhanced 7nm-class DUV multi-patterning process, without EUV, because ASML EUV tools are blocked by Dutch and US export controls. Yields are poor owing to process immaturity and equipment restrictions, so moving off the TSMC die bank requires redundant masks and die runs to hit Huawei's 2026 volume targets. Allen argues Huawei holds substantial influence over SMIC through government relationships and customer-scale purchasing, positioning Huawei to restrict competitors' access to domestic Chinese fabrication rather than only consume it (CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025)).
HBM as the binding constraint
Huawei's 2026 ramp is gated on HBM rather than on logic dies. CXMT, the domestic HBM supplier, is projected to deliver only about 2 million stacks in 2026, enough for roughly 250,000–300,000 910C units. Historical supply was supplemented by Samsung HBM stacks, estimated at about 11.4 million delivered to China, before the December 2024 BIS HBM controls. Huawei's longer-run response is proprietary memory architectures, HiBL and HiZQ, that decouple from standard HBM SKUs. (Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md; Source: Raw Sources/SemiAnalysis - CoWoS and HBM Supply Chain.md.)
CloudMatrix rack-scale systems
Huawei's systems-level response to per-chip performance gaps is to aggregate many 910Cs with optical interconnect into a single rack-scale pod. SemiAnalysis frames CloudMatrix 384 as China's answer to Nvidia's GB200 NVL72: more chips, more power, and competitive pod-level BF16 throughput. Huawei claims 95% efficiency at 8,000-supernode scale. This approach trades the silicon gap for system-level networking and more dies per workload, consistent with the assessment that China is about one generation behind on silicon but scaling on volume. (Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md.)
Comparison to Nvidia B200
| Dimension | Ascend 910C | Nvidia B200 |
|---|---|---|
| Per-die BF16 | ~⅓ B200 | 1.0× (reference) |
| Process | SMIC 7nm (+ TSMC legacy dies) | TSMC 4NP |
| Memory | HBM3 (CXMT / Samsung) | HBM3e (SK Hynix) |
| Packaging | Domestic 2.5D | TSMC CoWoS |
| Pod-scale competitor | CloudMatrix 384 | GB200 NVL72 |
| Availability inside China | Yes | Restricted (export controls) |
| Volume 2026 target | ~600k | Demand-unconstrained, supply-limited |
Software ecosystem
Allen identifies CANN, Huawei's compute architecture for neural networks, as the binding software chokepoint. Huawei's own employees described CANN as "difficult and unstable" as of September 2024, and DeepSeek's internal evaluation of it was "very negative." Allen uses Google's TensorFlow-to-JAX migration, which took two to three years, as a lower-bound proxy for time-to-maturity. On this reading, Huawei's silicon is catching up faster than its software ecosystem, and the SIMT/CUDA-compatibility additions in the 950 series are a tacit acknowledgment of the gap. Allen also identifies a forward-looking risk that DeepSeek's open-source community could accelerate CANN maturation by contributing kernels, fused operations, and broader framework support, closing the software gap without Huawei having to build it alone (CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025)).
DeepSeek partnership and domestic stack
Huawei's Ascend chips power Chinese AI models including DeepSeek's V4. Per DeepSeek's internal evaluation cited by Allen, the Ascend 910C delivers roughly 60% of H100 inference performance but is "unattractive for training"; with inference projected to reach 70% of total AI compute by 2026, Allen argues Ascend's strength lands where the workload mix is moving (CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025)).
On April 24, 2026, Huawei announced that the Ascend Supernode, based on the Ascend 950 chip, would fully support DeepSeek V4 inference, pairing the V4 model release with Huawei's rack-scale silicon. (Source: reuters.com)
On June 5, 2026, in an announcement by the Shenzhen government, a Huawei-led research team reported completing full-parameter post-training of DeepSeek's 1.6-trillion-parameter V4-Pro model on a cluster of at least 1,000 Ascend 910C chips, running more than 1,500 iterations without interruption. The result extends Chinese domestic silicon from inference toward large-scale training, the more compute-intensive half of the stack and the one US export controls most directly target, and is a datapoint on whether China can train frontier-scale models without Nvidia hardware. (Source: scmp.com) The pairing corresponds to the DeepSeek–Huawei domestic-stack flywheel Allen describes (see CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025), DeepSeek).
Strategic context
Ren Zhengfei coordinates an effort, described as "Spare Tire 2.0," spanning roughly 2,000 Chinese semiconductor firms plus about 30 advanced-lithography organizations, with reported effective "blank check" CCP backing. Its target is at least 70% Chinese semiconductor self-sufficiency across the full value chain by 2028. Analysts at RUSI, CETaS, American Affairs, and MERICS assess the target as plausibly attainable in mature nodes, packaging, and some DRAM, but unlikely at EUV, leading-edge logic, and HBM parity by 2028.
Allen's top-line forecast is that the US lead over China is unlikely to exceed "more than a year or two, even with extremely aggressive export controls," a conclusion he frames around Huawei's ramp rather than DeepSeek's algorithms as the load-bearing variable (CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025)).
Policy relevance
- Export controls: Ascend is a central test case. Controls have slowed but not stopped Huawei, and the binding chokepoint has migrated from logic, where SMIC is catching up, toward HBM and packaging.
- AI sovereignty: Ascend is an example of a nation partially building a sovereign compute stack.
- Compute governance: The Huawei case bears on compute-governance theory, in which chokepoints are nested and policy effectiveness tracks the weakest-link chokepoint rather than the headline one.
- AI race dynamics: Instantiates the "different races" thesis, in which China scales on volume and system-level networking while the per-chip frontier remains with Nvidia and TSMC.
The autonomous-driving compute commitment connects Huawei's Ascend program to Transportation — AI Deployment and AI Robotics.
Relationships
- depends-on: Semiconductor Supply Chain
- instance-of: AI Sovereignty (sovereign-compute-stack case)
- contradicts: Export Controls (AI) (unconditional-effectiveness framing)
- supports: AI Race Dynamics ("1 generation behind on silicon, scaling on volume")
- related: Nvidia & TSMC — AI Compute Infrastructure, DeepSeek, Compute Governance
Sources
- (Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md) — production ramp, die bank, HBM bottleneck
- (Source: Raw Sources/SemiAnalysis - CoWoS and HBM Supply Chain.md) — CoWoS/HBM context
- CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025) — Allen (CSIS, Mar 2025): geopolitical reading, TSMC die bank, CANN software chokepoint, DeepSeek-Huawei flywheel risk
- Stanford HAI AI Index Report 2026 — US-China compute / capability context