Semiconductor Supply Chain

The semiconductor supply chain for AI is the sequence of physical processes that converts silicon into AI accelerators and the rack-scale systems that house them. The stages run from silicon wafers through extreme ultraviolet (EUV) lithography, leading-edge fabrication, advanced packaging, high-bandwidth memory (HBM), accelerator-module assembly, and rack-scale integration. Each stage has a small set of suppliers, and the stages where supply is most concentrated function as chokepoints that constrain who can build the chips used to train frontier models. Analyses including Stanford HAI AI Index Report 2026 and SemiAnalysis argue that policy leverage from export controls, the CHIPS Act, and industrial policy attaches to those binding chokepoints rather than to the industry as a whole.

Stages of the chain

Silicon → EUV lithography → Leading-edge fabrication → Advanced packaging → HBM stacks → Accelerator module → Rack system
   ↓             ↓                     ↓                       ↓                ↓               ↓                 ↓
  SUMCO,       ASML              TSMC, Samsung,           TSMC (CoWoS),     SK Hynix,        Nvidia,        Dell, Foxconn,
  Shin-Etsu   (monopoly)         SMIC, Intel              OSATs              Samsung,         AMD,           Supermicro,
  (Japan)                                                                    Micron           Huawei         Huawei

EUV lithography. ASML (Netherlands) is the sole supplier of extreme ultraviolet lithography machines. Each tool costs roughly $200M and requires about 250 engineers and multi-year integration. EUV is required for leading-edge nodes (3nm and below, plus single-patterned 5nm/7nm). The tools have been export-controlled to China since 2019 under Dutch and US coordination.

Leading-edge fabrication. TSMC (Taiwan) is the dominant foundry and fabricates almost every frontier AI chip. Samsung Foundry (Korea) is the second player and holds an HBM integration advantage. Intel Foundry is behind on leading nodes and is pursuing 18A. SMIC (China), blocked from EUV, uses DUV multi-patterning to achieve "7nm-class" results at poor yield.

Advanced packaging (CoWoS). TSMC's CoWoS (Chip-on-Wafer-on-Substrate) is the 2.5D packaging that stitches logic dies to HBM stacks via a silicon interposer. Every Nvidia H-, B-, and GB-series and AMD MI-series accelerator requires CoWoS. CoWoS capacity ran at roughly 35k wafers per month in 2024, rose to about 70k in 2025, with a target of about 110k in 2026, and SemiAnalysis describes it as oversubscribed through at least 2026 (Source: Raw Sources/SemiAnalysis - CoWoS and HBM Supply Chain.md).

High-bandwidth memory (HBM). SK Hynix is the dominant HBM vendor, holding more than 95% HBM3 share at peak, was first to ship HBM3e and HBM4 in volume, and is the primary Nvidia supplier. Samsung is in second place; it historically struggled with Nvidia HBM3 qualification and was a major supplier to China before the December 2024 controls. Micron is third and ramped HBM3e later. As of 2026, all three vendors are essentially sold out under long-term contracts, with shortages projected into late 2027 (Source: Raw Sources/SemiAnalysis - CoWoS and HBM Supply Chain.md).

Accelerator assembly. Nvidia designs its accelerators, TSMC fabricates and packages them, and Nvidia and partners assemble the modules; AMD's MI-series follows the same pipeline. For Huawei Ascend, HiSilicon designs the chips, SMIC fabricates them (drawing also on a TSMC die bank), CXMT and Swaysure supply memory, and Huawei integrates.

Rack-scale systems. At the rack level, the comparison points are the Nvidia GB200 NVL72 and the Huawei CloudMatrix 384, which integrate optical interconnect, cooling, and power distribution. Assembly is handled by Foxconn, Supermicro, Dell, Wistron, and, for Ascend, Huawei.

Chokepoints

The stages where supply is most concentrated act as binding constraints on accelerator output. SemiAnalysis argues that through 2026 the binding chokepoints for AI accelerators are CoWoS and HBM rather than leading-edge logic, and that even Nvidia is packaging-constrained rather than fab-constrained (Source: Raw Sources/SemiAnalysis - CoWoS and HBM Supply Chain.md; Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md).

China's alternative stack

China began manufacturing domestically developed immersion DUV lithography machines in July 2026, with roughly five units due that year to SMIC, Hua Hong Semiconductor and ChangXin Memory Technologies and about 20 in 2027. These are the most advanced lithography tools available to Chinese fabs since EUV export restrictions; a domestic EUV tool remained at prototype stage (Source: reuters.com). Reuters restated the production start in its own reporting on July 28, 2026, attributed to a single source (Source: reuters.com). The development bears on the DUV-tools row of the chokepoint table above, where allied export policy had assumed no domestic Chinese substitute; both accounts rest on unnamed sourcing rather than a manufacturer announcement.

China is attempting to duplicate the chain domestically under "Spare Tire 2.0," a program associated with Ren Zhengfei and Huawei. Ren Zhengfei has set a target of 70% Chinese semiconductor self-sufficiency across the value chain by 2028. SemiAnalysis, RUSI, and CETaS assess this target as attainable in some segments (mature nodes, packaging, some DRAM) but unlikely in EUV and HBM parity (Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md, RUSI, CETaS). The status of the domestic alternatives as of 2026 is summarized below.

SemiAnalysis characterizes China's approach as not seeking per-chip parity but instead pursuing volume at the achievable node plus system-level aggregation, exemplified by CloudMatrix. The same source frames this as consistent with the different-races thesis, in which China optimizes for deployment and the US for frontier per-chip capability (Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md, China and the US Are Running Different AI Races).

Chinese chipmakers' international operations have also drawn regulatory scrutiny abroad: on July 17, 2026, South Korean competition authorities searched the offices of Chinese chipmaker Montage Technology (Source: reuters.com).

Relation to policy

Analyses of the chain hold that controls bind only to the extent they reach the binding chokepoint. SemiAnalysis reads the December 2024 BIS HBM rule as an implicit acknowledgment of this logic — HBM became a chokepoint and controls followed — and points to CoWoS packaging as the next candidate. These sources also describe export controls as nested: controlling chips without controlling HBM leaks capacity (China obtained roughly 11.4M Samsung HBM stacks before the December 2024 controls), and controlling logic but not packaging equipment leaks capacity differently.

The allied stack contains several single points of failure. ASML is one company in one country (the Netherlands); TSMC's CoWoS capacity is concentrated in one company on one island; and SK Hynix is the dominant HBM supplier with geographic concentration in Korea. A Taiwan Strait crisis would compound all three simultaneously.

On longer horizons, Toby Ord warns that controls may accelerate Chinese domestic capability-building over horizons of more than ten years, with the 2028 target of Spare Tire 2.0 as the test case.

Component-price inflation reached the official statistics in 2026. The US producer price index for electronic components and accessories rose 27.6% in June 2026 from a year earlier, the largest increase in a series running back to 1966, exceeding both the early-PC-era surge of 1980 and the pandemic-era chip shortage. Morgan Stanley, whose June note appears to have introduced the term "chipflation," found that memory prices had risen more than sixfold over the preceding year, and forecast a 0.10 percentage point increase in headline CPI for the year alongside a potential 15 percentage point increase in the CPI for PCs and smartphones. Apple is testing memory chips from the Chinese manufacturer CXMT and would need White House approval for such an arrangement, the Wall Street Journal reported on August 10, 2026 (Source: axios.com). The CXMT report bears on the alternative-stack table above, where CXMT is assessed as slightly behind on DRAM: the constraint on its adoption by a US buyer is described as regulatory rather than technical.

Industry has also pushed back on proposed US intervention in the memory market: chip industry group SEMI — whose members include Micron and Samsung — warned Treasury Secretary Scott Bessent in a letter reported July 2, 2026 that US intervention in chip pricing or capacity would worsen shortages (Source: bloomberg.com). Memory pricing has also drawn private litigation: Matt Stoller's July 4, 2026 round-up flagged a new class-action antitrust suit alleging price fixing by memory chipmakers (Source: thebignewsletter.com).

Relationships

• depends-on: Compute Governance (this concept is the physical substrate)
• supports: Export Controls (AI) (chokepoint mapping is the basis for control design)
• supports: AI Race Dynamics (different-races thesis)
• supports: AI Sovereignty (compute stack is the ceiling on sovereign AI)
• instance-of: None (this is a domain primitive)
• related: Nvidia & TSMC — AI Compute Infrastructure, Huawei — Ascend AI Accelerators

Wiki Sources

• (Source: Raw Sources/SemiAnalysis - CoWoS and HBM Supply Chain.md) — CoWoS/HBM chokepoint analysis
• (Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md) — Chinese alternative stack
• Stanford HAI AI Index Report 2026 — TSMC single-point-of-failure framing
• (Source: epochai.substack.com) — compute gap quantification