Huawei — Ascend AI Accelerators

Ascend is Huawei Technologies' line of AI accelerators, designed by its HiSilicon arm and fabricated primarily by SMIC. Built to supply Chinese AI compute after US export controls restricted Nvidia sales into China, the program spans the Ascend 910B and 910C chips, the 950 series, and the CloudMatrix rack-scale systems, with 960, 970 and 980 generations scheduled for 2027 through 2029. Its design integrates HiSilicon chip design, SMIC fabrication, CXMT/Swaysure memory, and proprietary CloudMatrix networking, and its production scale is constrained by high-bandwidth memory (HBM) supply rather than logic dies.

Snapshot

Production ramp

(Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md.)

Investment commitments

Deployment and ecosystem (company-reported)

Figures are from company materials as reported by Reuters and have not been independently verified.

Product roadmap

Dates in the table follow Huawei's two public roadmap disclosures: Eric Xu's Huawei Connect 2025 keynote of September 18, 2025, which scheduled the 950PR for the first quarter of 2026, the 950DT for the fourth quarter of 2026, the 960 for the fourth quarter of 2027 and the 970 for the fourth quarter of 2028 (Source: huawei.com), and the Huawei Connect 2026 revisions described below. The performance, process and memory columns follow SemiAnalysis's account of the 2025 roadmap (Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md).

The 950 series supports the FP32, HF32, FP16, BF16, FP8, MXFP8, HiF8, MXFP4, and HiF4 data formats. It also adds SIMT support to improve CUDA compatibility, addressing an adoption barrier against CUDA/PyTorch codebases. Some earlier reporting used the names "910PR / 910DT"; the official Huawei Connect 2025 nomenclature, from the Xu Zhijun keynote, is 950PR / 950DT.

Schedule changes and the 960 generation (Huawei Connect 2026)

At Huawei Connect in Shanghai on September 17, 2026, rotating chairman David Wang said the Ascend 960DT would be ready in the first quarter of 2027, three quarters earlier than previously planned, and the 960PR in the third quarter of 2027, one quarter ahead of schedule. Huawei intends to release a new generation of Ascend chips every year, with the 970 and 980 following in 2028 and 2029 (Source: reuters.com). The earlier plan, set out at Huawei Connect 2025, covered the 950PR, 950DT, 960 and 970 and placed the Ascend 960 in the fourth quarter of 2027 (Source: huawei.com). Rotating chairman Eric Xu said testing of the Ascend 950DT had produced good results, that Huawei was in extensive discussions with Chinese AI model developers, and that he expected many of them to begin training models on systems using the chip in 2027 (Source: reuters.com).

The conference also set out Huawei's systems approach of compensating for weaker individual chips by linking large numbers of processors. Huawei said clusters of about 100,000 chips have become standard for training some of the largest AI models and that communication between machines can consume more than 40% of training time in conventional server systems. It unveiled a computing architecture called Peerium, designed eventually to allow as many as 1 million processors to operate together as a single system, with its UnifiedBus technology connecting processors, memory, storage and networking equipment inside those systems. Huawei said its Ascend 960 supernode would connect as many as 4,096 AI processors, and that multiple supernodes could be linked into clusters of hundreds of thousands of processors, with the largest planned systems supporting as many as 1 million (Source: reuters.com). The 4,096 figure differs from the Atlas 960 SuperPoD that Huawei announced in September 2025 for the fourth quarter of 2027, which was to hold up to 15,488 Ascend 960 chips (Source: huawei.com); the September 2026 reporting does not relate the two figures. The Financial Times compared the 4,096-processor data-centre product with 1,024 processors in the previous generation, reported Huawei's statement that the new chips would deliver twice the computing performance of its current flagship, and wrote that the company has struggled to get AI laboratories to use its chips successfully for training large models (Source: ft.com).

Tau Scaling Law and LogicFolding

At a Shanghai semiconductor symposium on May 25, 2026, Huawei described a chip-design principle it calls the "Tau Scaling Law," arguing that the industry can no longer rely on shrinking transistors (the Moore-Dennard scaling tradition) and should instead optimize for shorter interconnects and lower in-chip data-movement latency. Huawei paired the principle with a specific architecture it calls "LogicFolding." The company said 381 chips had already been mass-produced on Tau Scaling principles at the time of the announcement, that Kirin smartphone chips launching later in 2026 would be the first to use LogicFolding as the architectural primitive, and that Ascend AI chips would adopt LogicFolding by 2030. Huawei set a target of transistor density equivalent to 1.4-nm processes by 2031 without access to the leading-edge EUV lithography that US export controls deny SMIC. SMIC shares rose 7.6% on the announcement. (Source: reuters.com; bloomberg.com)

Epoch AI's September 2026 assessment of that roadmap treats LogicFolding as Huawei's long-term answer to being held at 5–7 nm-class processes, and identifies its timing as the constraint: none of the Ascend chips before 2030 — the 950, 960, 970 or 980 — uses it, while Nvidia's Feynman is expected to stack at least two layers of 1.6 nm-class logic in 2028, two years earlier and two process nodes ahead (Will Huawei catch up to Nvidia by 2030? (Epoch AI, September 2026)). Epoch also sets out why hybrid bonding suits Huawei's constraints. Most of the tool steps that create a stack — wafer bonders, die-to-wafer bonders, temporary bonding and alignment, and chemical mechanical planarization — sit outside the export-control regime, while TSV deposition and fill are controlled, so in Epoch's summary "the path is open, but it narrows right where the engineering gets hard": the uncontrolled steps cover the two-layer stage Huawei is entering, and the controlled ones sit in front of improving yield and moving to three or more layers. Huawei reports a 54% density increase, a 41% power reduction and a 13% clock-speed gain on its folded 2026 Kirin chip; Epoch's caution on transferring that to an Ascend die is a yield calculation — at the same defect density, a 137 mm² Kirin die yielding 70% implies about 12% for an 800 mm² die, so roughly half of two-die Kirin stacks succeed against roughly 1% of stacks built from reticle-sized dies, before bonding failures — and a thermal one, a phone chip drawing perhaps 10 W against an Ascend's hundreds.

The roadmap describes a path that does not require EUV access, and the latency-optimization framing aligns with the inference-cost compression argument that Dario Amodei of Anthropic has emphasized as a scaling frontier (see AI cybersecurity). The symposium came alongside the government-to-government AI dialogue Xi Jinping and Donald Trump agreed to launch during Trump's May 2026 China visit. In the same week at Taipei, Nvidia CEO Jensen Huang said Nvidia has "largely conceded" China's AI-chip market to Huawei. (Source: reuters.com; bloomberg.com)

Fabrication and supply chain

TSMC die bank

Before the October 2020 entity-list tightening, Huawei/HiSilicon stockpiled more than 2.9 million advanced Ascend dies fabricated at TSMC. SemiAnalysis classifies this stockpile as an export-control violation, and it funded 2024 and most of 2025 production. TechInsights teardowns confirm that deployed 910C units still contain TSMC CPU dies dated 2020. (Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md.) Gregory Allen's CSIS report confirms via US government sources that TSMC manufactured 2 million-plus Ascend 910B logic dies for Huawei through shell companies, which Allen describes as a "strategically significant stockpile" and a direct export-control violation; SemiAnalysis's 2.9 million figure is consistent with, and higher than, Allen's more conservative government-sourced number. Allen assesses that the stockpile materially extended Huawei's runway through 2024–2025 (Gregory Allen's CSIS report).

SMIC collaboration

SMIC fabricates Ascend logic on an enhanced 7nm-class DUV multi-patterning process, without EUV, because ASML EUV tools are blocked by Dutch and US export controls. Yields are poor owing to process immaturity and equipment restrictions, so moving off the TSMC die bank requires redundant masks and die runs to hit Huawei's 2026 volume targets. Allen argues Huawei holds substantial influence over SMIC through government relationships and customer-scale purchasing, positioning Huawei to restrict competitors' access to domestic Chinese fabrication rather than only consume it (CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025)).

HBM as the binding constraint

Huawei's 2026 ramp is gated on HBM rather than on logic dies. CXMT, the domestic HBM supplier, is projected to deliver only about 2 million stacks in 2026, enough for roughly 250,000–300,000 910C units. Historical supply was supplemented by Samsung HBM stacks, estimated at about 11.4 million delivered to China, before the December 2024 BIS HBM controls. Huawei's longer-run response is proprietary memory architectures, HiBL and HiZQ, that decouple from standard HBM SKUs. (Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md; Source: Raw Sources/SemiAnalysis - CoWoS and HBM Supply Chain.md.)

CloudMatrix rack-scale systems

Huawei's systems-level response to per-chip performance gaps is to aggregate many 910Cs with optical interconnect into a single rack-scale pod. SemiAnalysis frames CloudMatrix 384 as China's answer to Nvidia's GB200 NVL72: more chips, more power, and competitive pod-level BF16 throughput. Huawei claims 95% efficiency at 8,000-supernode scale. This approach trades the silicon gap for system-level networking and more dies per workload, consistent with the assessment that China is about one generation behind on silicon but scaling on volume. (Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md.)

Comparison to Nvidia B200

Software ecosystem

Allen identifies CANN, Huawei's compute architecture for neural networks, as the binding software chokepoint. Huawei's own employees described CANN as "difficult and unstable" as of September 2024, and DeepSeek's internal evaluation of it was "very negative." Allen uses Google's TensorFlow-to-JAX migration, which took two to three years, as a lower-bound proxy for time-to-maturity. On this reading, Huawei's silicon is catching up faster than its software ecosystem, and the SIMT/CUDA-compatibility additions in the 950 series are a tacit acknowledgment of the gap. Allen also identifies a forward-looking risk that DeepSeek's open-source community could accelerate CANN maturation by contributing kernels, fused operations, and broader framework support, closing the software gap without Huawei having to build it alone (CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025)).

Huawei's own account in September 2026 was that the software gap has narrowed from the other direction, through changes in training practice rather than through CANN alone. Heng Liao, chief scientist of Huawei's semiconductor division, said in remarks reported on September 17, 2026 that changes in how increasingly large and complex models are trained were eroding the advantage of Nvidia's CUDA platform: "CUDA is not as important as it was two years ago," he said, pointing to new programming tools and training approaches, and "the software gap is greatly diminished" (Source: ft.com). The statement is the vendor's assessment; the same account reports that Huawei has struggled to get AI laboratories to train large models on its chips.

DeepSeek partnership and domestic stack

Huawei's Ascend chips power Chinese AI models including DeepSeek's V4. Per DeepSeek's internal evaluation cited by Allen, the Ascend 910C delivers roughly 60% of H100 inference performance but is "unattractive for training"; with inference projected to reach 70% of total AI compute by 2026, Allen argues Ascend's strength lands where the workload mix is moving (CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025)).

On April 24, 2026, Huawei announced that the Ascend Supernode, based on the Ascend 950 chip, would fully support DeepSeek V4 inference, pairing the V4 model release with Huawei's rack-scale silicon. (Source: reuters.com)

On June 5, 2026, in an announcement by the Shenzhen government, a Huawei-led research team reported completing full-parameter post-training of DeepSeek's 1.6-trillion-parameter V4-Pro model on a cluster of at least 1,000 Ascend 910C chips, running more than 1,500 iterations without interruption. The result extends Chinese domestic silicon from inference toward large-scale training, the more compute-intensive half of the stack and the one US export controls most directly target, and is a datapoint on whether China can train frontier-scale models without Nvidia hardware. (Source: scmp.com) The pairing corresponds to the DeepSeek–Huawei domestic-stack flywheel Allen describes (see CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025), DeepSeek).

Strategic context

Ren Zhengfei coordinates an effort, described as "Spare Tire 2.0," spanning roughly 2,000 Chinese semiconductor firms plus about 30 advanced-lithography organizations, with reported effective "blank check" CCP backing. Its target is at least 70% Chinese semiconductor self-sufficiency across the full value chain by 2028. Analysts at RUSI, CETaS, American Affairs, and MERICS assess the target as plausibly attainable in mature nodes, packaging, and some DRAM, but unlikely at EUV, leading-edge logic, and HBM parity by 2028.

Huawei's own account of its position is that demand exceeds supply. Eric Xu said on September 17, 2026 that Huawei cannot produce enough AI computing equipment to meet demand in China and is therefore limiting overseas sales: "Since we don't have enough capacity to even satisfy the demand in China, we don't have a plan to expand into the international market in a fully-fledged way," with limited volumes supplied to some countries where demand is particularly strong. Calling reliable data on Nvidia's share of China's AI chip market difficult to obtain, he said "I think Ascend market share should be bigger than Nvidia's"; Huawei did not provide data to support the estimate. Xu linked the program to self-sufficiency ("We cannot accept a destiny where we cannot control our fate being determined by others in terms of willingness to sell chips to China or not"), and Guo Ping, chairman of Huawei's supervisory board, told employees in remarks released the same week that the company viewed AI as its "biggest opportunity" and wanted its computing and connectivity infrastructure to play a role comparable to Nvidia's (Source: reuters.com). Xu's estimate concerns market share inside China, the market Jensen Huang said in May 2026 Nvidia had "largely conceded" to Huawei; it is a different quantity from the production comparison in Epoch AI's report below, which measures Huawei's total AI compute output against Nvidia's worldwide.

Xu also addressed the pace of Chinese model development at a press conference on September 17. He acknowledged that Huawei remained "not as advanced" as leading US rivals and urged Chinese AI companies to accelerate development to catch up with frontier US laboratories, saying Chinese researchers needed to "increase the speed of development so they can also see the dangers of AI development" like their US counterparts, and that once those risks emerged the industry would need to "strike a balance between driving development and risks." He said at least six or seven Chinese AI laboratories aimed over the next two years to train models containing 10tn to 40tn parameters, which the Financial Times described as a significant increase from current model sizes in China (Source: ft.com). The Financial Times noted that the remarks came days after Anthropic and OpenAI called for a coordinated slowdown; they were made the same day the Washington Post reported Rep. Ro Khanna's letters asking Chinese laboratories to join a pacing agreement; see Coordinated slowdown proposals compared and Khanna letter to Alibaba on pacing the frontier (September 16, 2026).

Allen's top-line forecast is that the US lead over China is unlikely to exceed "more than a year or two, even with extremely aggressive export controls," a conclusion he frames around Huawei's ramp rather than DeepSeek's algorithms as the load-bearing variable (CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025)).

Epoch AI reached a more pessimistic assessment of the ramp. In a report published September 12, 2026, researcher Venkat Somala analysed Huawei's chip roadmap through 2031 and found that Huawei's most powerful chip delivers roughly half the arithmetic performance of Nvidia's H100, which Nvidia began shipping in 2022. Epoch estimates Huawei will produce 0.9 million H100-equivalents in 2026 against Nvidia's 23 million — under 4% of Nvidia's AI compute — and concludes that export controls constrain both levers Huawei could use to close the gap, making it unlikely Huawei will catch Nvidia this decade (Will Huawei catch up to Nvidia by 2030? (Epoch AI, September 2026); Source: epochai.substack.com).

The report's percentages are outputs of one model under different inputs rather than a single forecast, and each carries its condition. Under 4% is the 2026 figure. Around 1% by 2028 holds only if Huawei uses domestically produced HBM alone. About 11% in 2028 is the figure under a smuggling scenario at ten times domestic supply — a flow Epoch calls implausibly large, over $40 billion at a conservative $15 per gigabyte — which it offers to show that smuggling moves the number materially without closing the gap. The 17.5× per-chip gap Epoch projects for 2027 is a specification comparison rather than a ratio of delivered compute (Will Huawei catch up to Nvidia by 2030? (Epoch AI, September 2026)).

Its substantive finding is that the binding constraint moves. Decomposing the 2026 gap, Nvidia secures 32× the HBM wafer starts and yields 2.3× more usable memory per wafer — 73× more usable HBM — while its chip mix pairs 2.7× as much compute with each gigabyte, compounding to roughly 200× in compute throughput and 71× in aggregate bandwidth. By 2028 the compute gap narrows to about 100×, but its composition inverts: the usable-HBM gap falls from 73× to 11× as CXMT and XMC complete their ramp and improve yields, while Nvidia's advantage in compute per gigabyte rises from 2.7× to 9× as production shifts to Rubin Ultra. As China's memory supply expands, the limit on Huawei's output stops being how much memory it can obtain and becomes how much compute it can attach to it — and Epoch notes that pairing more compute with each gigabyte would require more logic per chip, moving the bottleneck again to SMIC's wafer output (Will Huawei catch up to Nvidia by 2030? (Epoch AI, September 2026)).

On the roadmap itself, Epoch's reading is that Huawei's projected doubling of per-chip performance in each of the next two generations cannot come from the process node: the 950 and 960 are fabricated on SMIC's N+3 and the 970 likely on N+4, both 5–7 nm-equivalent DUV processes whose transition raises transistor density by about 20%, so the projected 4× must come from larger dies, more dies per package, or both. It characterises the near-term plan as "largely a packaging roadmap rather than a process-node roadmap," with the corresponding exposure to yield and packaging failure as packages grow larger and more valuable (Will Huawei catch up to Nvidia by 2030? (Epoch AI, September 2026)).

Epoch's conclusion and Gregory Allen's differ in kind as much as in degree. Allen's forecast concerns the gap between US and Chinese AI capability and treats Huawei's ramp as the load-bearing variable; Epoch's concerns the gap between Huawei and Nvidia in delivered AI compute, and reads export controls as binding on both the per-chip performance lever and the production-volume lever at once. The two are compatible if Chinese developers close capability gaps on substantially less compute, which is the premise the DeepSeek line of argument rests on.

Policy relevance

• Export controls: Ascend is a central test case. Controls have slowed but not stopped Huawei, and the binding chokepoint has migrated from logic, where SMIC is catching up, toward HBM and packaging.
• AI sovereignty: Ascend is an example of a nation partially building a sovereign compute stack.
• Compute governance: The Huawei case bears on compute-governance theory, in which chokepoints are nested and policy effectiveness tracks the weakest-link chokepoint rather than the headline one.
• AI race dynamics: Instantiates the "different races" thesis, in which China scales on volume and system-level networking while the per-chip frontier remains with Nvidia and TSMC.

The autonomous-driving compute commitment connects Huawei's Ascend program to Transportation — AI Deployment and AI Robotics.

Relationships

• depends-on: Semiconductor Supply Chain
• instance-of: AI Sovereignty (sovereign-compute-stack case)
• contradicts: Export Controls (AI) (unconditional-effectiveness framing)
• supports: AI Race Dynamics ("1 generation behind on silicon, scaling on volume")
• related: Nvidia & TSMC — AI Compute Infrastructure, DeepSeek, Compute Governance
• related: US-China AI Competition: Different Races, Different Metrics — Huawei's schedule and supply claims in the US-China context
• related: Coordinated slowdown proposals compared — Xu's September 2026 call for Chinese laboratories to accelerate rather than slow

Sources

• (Source: reuters.com) — Reuters (Sept 17, 2026): Huawei Connect 2026 schedule changes, Peerium, Ascend 960 supernode, Xu and Guo Ping remarks, company-reported deployment figures
• (Source: huawei.com) — Huawei (Sept 18, 2025): Eric Xu's Huawei Connect 2025 keynote with the original 950–970 schedule and Atlas SuperPoD sizes
• (Source: ft.com) — Financial Times (Sept 17, 2026): Xu's call for Chinese laboratories to accelerate, the 10tn–40tn-parameter ambitions, Heng Liao on CUDA, 4,096- versus 1,024-processor systems
• Will Huawei catch up to Nvidia by 2030? (Epoch AI, September 2026) — Epoch AI (Sept 2026): compute-output model, where the HBM-versus-performance constraint moves, LogicFolding timing
• (Source: Raw Sources/SemiAnalysis - Huawei Ascend Production Ramp.md) — production ramp, die bank, HBM bottleneck
• (Source: Raw Sources/SemiAnalysis - CoWoS and HBM Supply Chain.md) — CoWoS/HBM context
• CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025) — Allen (CSIS, Mar 2025): geopolitical reading, TSMC die bank, CANN software chokepoint, DeepSeek-Huawei flywheel risk
• Stanford HAI AI Index Report 2026 — US-China compute / capability context