A report published September 12, 2026 by Venkat Somala of Epoch AI. It assesses the AI chip roadmap Huawei set out in a keynote at IEEE ISCAS 2026 against Nvidia's, and concludes that Huawei will not close the gap this decade. Its stated premise is that Huawei is a useful proxy for China's progress toward indigenizing AI compute production, which is what semiconductor export controls are aimed at.
The report is an assessment of Huawei's published roadmap rather than an independent account of it, and its estimates rest on an explicit model whose inputs, confidence intervals and notebooks are published alongside it. Its own title is "Will Huawei catch up to Nvidia by 2030?"; "Huawei's Roadmap to 2031" is the URL slug and the name some coverage uses.
What the report measures
The comparison is made in delivered compute rather than chip counts. Each chip's total processing power is expressed as a number of Nvidia H100 GPUs (H100-equivalents, or H100e) and multiplied by units produced, so that a large volume of weaker chips and a small volume of stronger ones can be placed on one scale. The report states the limits of the measure: it is an on-paper comparison that does not account for memory, scale-up domain, workload shape, interactivity or software, and Huawei's realized performance is likely below what the H100e figure implies because its CANN software stack is far less mature than Nvidia's CUDA.
Position in 2026
Huawei's 2026 flagship is the Ascend 950, in two variants sharing a compute die. The 950PR, in mass production from the first quarter of 2026, carries 128 GB of memory at 1.6 TB/s and is optimized for the prefill stage of inference; the 950DT, slated for the fourth quarter, carries 144 GB at 4 TB/s. The report reads this split as a memory-supply adaptation: prefill is compute-intensive and less bandwidth-bound than decode, so Huawei pairs the more available low-bandwidth memory with prefill and reserves scarce high-bandwidth memory for the decode-oriented part. It also notes that Huawei shrank the logic footprint from two roughly 665 mm² dies on the 910C to two roughly 400 mm² dies, most likely for yield, since the 950 depends far more heavily on SMIC fabrication than the 910C, whose logic dies reportedly came largely from TSMC.
On specifications the Ascend 950DT delivers 1 PFLOP of FP8, "roughly half the Nvidia H100" — a chip that began shipping in 2022 — which is the basis for the report's claim that Huawei's chip performance trails Nvidia's by about four years. Against Nvidia's current B300 the FP4 peak gap is 6.75× (13.5 PFLOPS against 2), which the report decomposes into roughly 1.6× from process-node density, 2.0× from logic silicon area, and 2.1× from performance per transistor (clock speed, FP4 datapaths, tensor-core design, power envelope). On performance per dollar the gap narrows to about 3.4×, assuming roughly $20,000 for the 950DT against roughly $40,000 for the B300; on bandwidth per dollar the two are roughly tied at 0.2 GB/s per dollar.
On volume, Epoch estimates Huawei produced 800,000 Ascend units in 2025 against Nvidia's 4.5 million, and projects 1.5 million against 5.9 million in 2026 — a median matching a Wall Street Journal report of Huawei's own expectation. The 2026 mix is modelled by memory channel: roughly 750,000 950PRs on non-HBM memory sourced domestically, 430,000 910Cs on the remaining Samsung stockpile and 2025 smuggled supply, 240,000 950DTs on CXMT and XMC high-bandwidth memory, and 80,000 950DTs on smuggled supply.
Combined, that is 880,000 H100-equivalents for Huawei against 23 million for Nvidia — under 4% of Nvidia's output in 2026, reaching 6% at the extremes of the confidence intervals. Volume accounts for roughly a quarter of the gap and per-chip performance for roughly seven times, compounding to about 25×.
Why the roadmap does not close the gap
Huawei's roadmap projects a doubling of per-chip performance in each of the next two generations, from the Ascend 950 to the Ascend 970 in 2028. The report's central technical observation is that this cannot come from the process node. The 950 and 960 compute dies are fabricated on SMIC's N+3 process and the 970 likely moves to N+4; both are 5–7 nm-equivalent DUV processes, and the N+3-to-N+4 transition is expected to raise transistor density by only about 20%. The projected 4× must therefore come from larger dies, more dies per package, or both — making Huawei's near-term performance roadmap "largely a packaging roadmap rather than a process-node roadmap," with the corresponding exposure to yield and packaging failure as packages grow more valuable.
Nvidia is pulling the same levers from a denser base. SMIC's leading N+3 node delivers about 113 million transistors per mm² against about 224 million for TSMC's N3P, and the report projects roughly 2× density advantage persisting through 2030 as TSMC moves to A16 in 2028 and A14 in 2029 while SMIC moves to N+4 and N+5. Nvidia also adds a dimension Huawei will not have until 2030: its Feynman generation, expected in 2028, is reported to use 3D-stacked logic on A16, giving an effective planar density above 500 MTr/mm² against the Ascend's 137 MTr/mm² on N+4 — widening a 2× process gap to nearly 4× — with TSMC's CoWoS packaging roadmap growing from 5.5-reticle packages in 2026 to 14× in 2028 to place more of those denser stacked dies side by side.
On memory, Huawei projects per-chip bandwidth rising from 4 TB/s on the 950DT to 14.4 TB/s on the Ascend 970 in late 2028, which the report reads as an expectation that Chinese suppliers will reach between HBM3E and HBM4. Nvidia moves from 8 TB/s on Blackwell to 22 TB/s on Rubin and is developing custom HBM base dies that it claims deliver 30% more bandwidth than HBM4E, 15% lower memory power and 25% more available compute die area.
The report's conclusion on performance is that the point-in-time gap widens before it narrows: from roughly 7× today to roughly 17.5× next year on paper as Rubin and Rubin Ultra arrive. The first Ascend expected to approach the B200's peak performance is the 970 in late 2028, and the B200 arrived in late 2024 — leaving Huawei roughly four years behind at the chip level even out to 2029.
Systems and software
The report treats scale-up networking as the area where Huawei is most competitive. Its CloudMatrix 384 connects 384 chips across 16 racks with a non-blocking optical fabric at 400 GB/s per chip, against 72 GPUs in Nvidia's NVL72; the Atlas 950 SuperPoD, due in the fourth quarter of 2026, connects 8,192 chips, and the Atlas 960 SuperPoD 15,488 in 2027.
It argues the two numbers are not comparable. Nvidia builds a fabric in which any GPU can reach any other at full bandwidth inside the rack and accepts a roughly 9× bandwidth cliff at the rack boundary, relying on software to keep communication-intensive work local. Huawei cannot build a non-blocking fabric at 8,192 chips and instead uses a hierarchy — 64 chips per rack, 16 racks per 1,024-chip pod, 8 pods to reach 8,192 — so its headline 1 TB/s per chip measures injection bandwidth into a shared network rather than guaranteed chip-to-chip bandwidth, and performance becomes dependent on where a chip sits, on workload shape and on software. Huawei does not publish bisection or pairwise bandwidth, which the report says are the figures needed to assess the design.
It identifies wide expert parallelism as the workload shape that would suit large pods: sparse mixture-of-experts models spread across more chips give each chip fewer experts to hold, compensating for weaker per-chip performance, and the traffic is dominated by very small messages — 96% of them two bytes, per Huawei — so throughput depends more on message rate than link width. The report's judgment is that scale-up "is not a substitute for closing the per-chip performance gap," and that the evidence from production workloads is insufficient to assume system engineering erases the hardware disadvantage.
On software, it records that CANN, first released in 2018, remains years behind CUDA, and that when DeepSeek attempted to train its R2 model on Ascend, Huawei sent its own engineers and the training run still could not be completed, prompting a reversion to Nvidia. It also sets out the mechanism by which that could change: Nvidia's software advantage comes substantially from a feedback loop with frontier developers who expose bottlenecks, and Chinese laboratories — pushed onto Ascend by export controls, incentivized by compute scarcity, and more inclined to open-source and to contribute back — could create the same flywheel for Huawei. The report calls the flywheel nascent, noting that Chinese labs still reach for Nvidia hardware when they can get it.
The volume question, and where the constraint moves
The report's most specific contribution concerns which constraint binds, and when.
Chinese domestic production is currently limited by high-bandwidth memory. A stockpile of more than 10 million foreign HBM stacks built up before the December 2024 export controls — enough for roughly 1–2 million Ascend chips — filled the 2025 gap and is modelled as fully spent in 2026, which the report calls an inflection year.
Modelling CXMT and XMC as Huawei's only HBM sources, using SemiAnalysis wafer-start estimates and Huawei allocations falling from 75% of CXMT's output in 2026 to 65% in 2028 as Cambricon, Biren, Baidu and Alibaba compete for it, Epoch estimates Huawei reaching around 1 million H100-equivalents by 2028, roughly 1% of Nvidia's output, with the gap exceeding 20× even at the extremes of its confidence intervals. Measured in memory bandwidth rather than compute throughput the position is better — 0.3 million H100-bandwidth-equivalents in 2026 rising to 2.8 million in 2028, or 1.4% rising to 3.2% — which the report attributes to bandwidth having historically improved more slowly than compute.
Extending to 2030 under an optimistic assumption of 2 million DRAM wafer starts per month with 30% allocated to HBM, an 18× increase over end-2026, a back-of-the-envelope calculation gives Huawei 12–18 million H100-equivalents in 2030, still only 12–18% of Epoch's median for Nvidia's 2028 production. Put another way: even with Nvidia's output frozen at its 2028 level, it would still be 7× Huawei's 2030 output.
Smuggling moves the number without closing the gap. If Huawei smuggled ten times as much HBM as its entire domestic supply in 2028 — a flow the report calls implausibly large, over $40 billion at a conservative $15 per GB — its output would rise from just under 1 million H100e to roughly 11 million, about 11% of Nvidia's production that year. Extending the 950PR's non-HBM approach to more products is the other available channel, at the cost of bandwidth and therefore of the workloads the chip suits; Huawei's published memory roadmap through 2029 shows no intention of doing so, though the report notes that Nvidia itself is reported to be testing lower-memory Rubin Ultra configurations as memory costs rise.
Where the binding constraint sits changes around 2028. Decomposing the gap into HBM wafer capacity secured, yielded gigabytes per wafer, and compute paired with each gigabyte, the 2026 picture is dominated by memory access: Nvidia secures 32× the wafer starts and yields 2.3× more usable memory per wafer, 73× more usable HBM in total, while its 2026 chip mix packs 2.7× as much compute per gigabyte — compounding to a roughly 200× gap in compute throughput and 71× in bandwidth. By 2028 the compute gap shrinks to about 100×, but the composition inverts: the usable-HBM gap narrows from 73× to 11× as CXMT and XMC ramp and improve yields, while Nvidia's advantage in compute per gigabyte grows from 2.7× to 9× as production shifts to Rubin Ultra. As China's memory supply expands, in other words, the limit on Huawei's output stops being how much memory it can get and becomes how much compute it can attach to it. The report flags that pairing more compute with each gigabyte requires more logic per chip, which would move the bottleneck again — to SMIC's wafer output.
LogicFolding
Huawei's long-term answer to the density ceiling is to build upward. LogicFolding stacks logic dies vertically so that 5–7 nm-class transistors distributed across two or more layers reach the planar density of a far more advanced node; Huawei's stated aim is two stacked 5 nm-class dies reaching the equivalent density of a 1.4 nm process by 2031. The report identifies three claimed benefits: density; shorter critical paths, since a logic block split across bonded tiers replaces long horizontal wires with short vertical hops and needs fewer buffers; and, if memory rather than logic is stacked on the logic die, relief from what Huawei calls the N²-versus-N fan-out dilemma, in which compute scales with die area while the edge interfaces that feed it scale only with die perimeter.
It also identifies why Huawei chose this route. Hybrid bonding, which LogicFolding depends on, fits China's comparative strengths: packaging has long been outsourced to Chinese firms including JCET, Tongfu and Huatian, and YMTC already uses hybrid bonding for NAND. The report's appendix maps the tool flow and finds that most of the steps that actually create a stack — wafer bonders, die-to-wafer bonders, temporary bonding and alignment, and the chemical mechanical planarization that polishes the bond surface — sit outside the export-control regime, while TSV deposition and fill are controlled. Its summary is that "the path is open, but it narrows right where the engineering gets hard": the uncontrolled steps cover the two-layer stage Huawei is entering, and the controlled ones sit in front of improving yield and moving to three or more layers.
The timing is the report's substantive finding. No Ascend before 2030 uses LogicFolding — not the 950, 960, 970 or 980. Huawei will instead mature the process on Kirin smartphone chips, where a 2026 folded part reports a 54% density increase, a 41% power reduction and a 13% clock-speed increase. The report explains why a phone chip is the right proving ground and why the transfer is not straightforward: at the same defect density, a 137 mm² Kirin die yielding 70% implies about 12% for an 800 mm² die, so about half of two-die Kirin stacks succeed against roughly 1% of stacks built from reticle-sized dies, before bonding failures; and a phone chip drawing perhaps 10 W presents a far easier thermal problem than an Ascend drawing hundreds. Huawei's own Kirin density roadmap rises from 155 MTr/mm² in 2025 to 238 in 2026 with the first two-layer fold, then by roughly 5% a year to 292 by 2030, before jumping to 400 in 2031 — a curve the report reads as two layers approaching their ceiling of roughly 310 MTr/mm² with the 2031 step implying more tiers or wider application.
Against that, Nvidia's Feynman is expected to stack at least two layers of 1.6 nm-class logic in 2028, two years before the first folded Ascend and on a process two nodes ahead.
Conclusion and its scope
The report's closing assessment is that Huawei began 2026 producing roughly 25× less AI compute than Nvidia, that its chips are three to four years behind, and that export controls act on both dimensions of the competition at once — on volume through HBM and lithography access, and on performance through the process node. It does not treat the outcome as fixed: Huawei "may eventually catch up — by outperforming Nvidia on vertical stacking, improving its software dramatically enough to close the utilization gap with CUDA, gaining access to a cutting-edge process node, and significantly scaling production," but "the available information suggests it's unlikely to happen by 2030."
The percentages are conditional and should be quoted with their conditions. "Under 4%" is 2026. "Around 1% by 2028" holds only under domestic HBM alone. "About 11%" is the 2028 figure under a smuggling scenario at ten times domestic supply. The 17.5× per-chip figure is a specification comparison rather than a delivered-compute ratio.
Provenance
Published on Epoch AI's publications path on September 12, 2026; captured complete, including all 34 footnotes, on September 13, 2026. Somala is a researcher at Epoch AI. The compute-production models for both companies are published as Colab notebooks and the parameter set as a spreadsheet, and the report is released under CC-BY. Acknowledgements name Jack Freed, Hamish Low, Saif Khan, JS Denain, Isabel Juniewicz and Josh You. Confidence is high: the modelling assumptions, inputs and confidence intervals are published and the underlying supply-chain estimates are attributed, chiefly to SemiAnalysis.
Relationships
- related: Huawei — Ascend AI Accelerators — the subject
- related: Nvidia & TSMC — AI Compute Infrastructure — the comparator
- related: Epoch AI — publisher
- supports: Export Controls (AI) — assesses export controls as binding on both the performance and the volume lever
- supports: Chip Smuggling and Export-Control Evasion — quantifies a ceiling on what smuggling could achieve
- related: Semiconductor Supply Chain
- related: CSIS — DeepSeek, Huawei, Export Controls, and the Future of the U.S.-China AI Race (Allen, March 2025) — reaches a markedly less favourable assessment of Huawei's trajectory; the two measure different quantities and are compatible only under conditions set out on Huawei — Ascend AI Accelerators